Verifying Safety Properties of a PowerPC 1 Microprocessor Using Symbolic Model Checking without BDDs

In [2] Bounded Model Checking with the aid of satis ability solving (SAT) was introduced as an alternative to traditional symbolic model checking based on solving xpoint equations with BDDs. In this paper we show how bounded model checking can take advantage of specialized optimizations. We present a bounded version of the cone of in uence reduction that works very well for verifying safety properties. We have successfully applied this idea to checking safety properties of a PowerPC microprocessor under design at Motorola's Somerset PowerPC design center. Based on that experience, we propose a veri cation methodology that we feel can bring model checking into the mainstream of industrial chip design.